Low leakage MIM capacitor

ABSTRACT

Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxide buffer layer interposed between the dielectric layer and at least one of the bottom and top electrodes. Each metal oxide buffer layer acts to improve capacitance and reduce capacitor leakage. The capacitors are suited for use as memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

TECHNICAL FIELD

[0001] The present invention relates generally to metal-insulator-metalsemiconductor capacitors, and in particular to development ofsemiconductor capacitor structures having a buffer layer, and apparatusincluding such capacitor structures.

BACKGROUND

[0002] Many electronic systems include a memory device, such as aDynamic Random Access Memory (DRAM), to store data. A typical DRAMincludes an array of memory cells. Each memory cell includes a capacitorthat stores the data in the cell and a transistor that controls accessto the data. The capacitor typically includes two conductive electrodesseparated by a dielectric layer. The charge stored across the capacitoris representative of a data bit and can be either a high voltage or alow voltage. Data is stored in the memory cells during a write mode andretrieved from the memory cells during a read mode. The data istransmitted on signal lines, sometimes referred to as digit lines, whichare coupled to input/output (I/O) lines through transistors used asswitching devices. Typically, for each bit of data stored, its truelogic state is available on an I/O line and its complementary logicstate is available on an I/O complement line. However, each such memorycell is coupled to, or associated with, only one digit line of a digitline pair through an access transistor.

[0003] Typically, the memory cells are arranged in an array and eachcell has an address identifying its location in the array. The arrayincludes a configuration of intersecting conductive lines, and memorycells are associated with the intersections of the lines. In order toread from or write to a cell, the particular cell in question must beselected, or addressed. The address for the selected cell is representedby input signals to a word line or row decoder and to a digit line orcolumn decoder. The row decoder activates a word line in response to theword line address. The selected word line activates the accesstransistors for each of the memory cells in communication with theselected word line. The column decoder selects a digit line pair inresponse to the digit line address. For a read operation, the selectedword line activates the access transistors for a given word lineaddress, the charge of the selected memory cells, i.e the charge storedin the associated capacitor, are shared with their associated digitlines, and data is sensed and latched to the digit line pairs.

[0004] As DRAMs increase in memory cell density by decreasing memorycell area, there is an ongoing challenge to maintain sufficiently highstorage capacitance despite decreasing memory cell area and itsaccompanying capacitor area, since capacitance is generally a functionof electrode area. Additionally, there is a continuing goal to furtherdecrease memory cell area.

[0005] A principal method of increasing cell capacitance is through cellstructure techniques. Such techniques include three-dimensional cellcapacitors, such as trenched or stacked capacitors. One common form ofstacked capacitor structure is a cylindrical container stackedcapacitor, with a container structure forming the bottom electrode ofthe capacitor. Such container structures may have shapes differing froma substantially cylindrical form, such as an oval or otherthree-dimensional container. The container structures may furtherincorporate fins.

[0006] Another method of increasing cell capacitance is through the useof high dielectric constant material in the dielectric layer of thecapacitor. In order to achieve the charge storage efficiency generallyneeded in 256 megabit (Mb) memories and above, materials having a highdielectric constant, and typically dielectric constants greater than 20,can be used in the dielectric layer between the bottom electrode and thetop electrode of the capacitor. The dielectric constant is acharacteristic value of a material and is generally defined as the ratioof the amount of charge that can be stored in the material when it isinterposed between two electrodes relative to the charge that can bestored when the two electrodes are separated by a vacuum.

[0007] Unfortunately, high dielectric constant materials are oftenincompatible with existing processes. One cause of such incompatibilitycan be adverse chemical reactions or oxygen diffusion between thematerial of the dielectric layer and the material of an adjoiningelectrode due to direct contact.

[0008] For the reasons stated above, and for other reasons which willbecome apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art foralternative capacitor structures and methods for producing same.

SUMMARY

[0009] The above mentioned problems with capacitors and associatedmemory devices, and other problems are addressed by the presentinvention and will be understood by reading and studying the followingspecification.

[0010] Embodiments of the invention include capacitors having a metaloxide buffer layer interposed between an electrode and a dielectriclayer, and methods of their formation. The metal oxide buffer layer actsto reduce undesirable charge leakage from the capacitor.

[0011] For one embodiment, the invention includes a capacitor. Thecapacitor includes two electrodes and a dielectric layer interposedtherebetween. The capacitor further includes a metal oxide buffer layerinterposed between the dielectric layer and one of the electrodes.

[0012] For one embodiment, the bottom electrode, the top electrode orboth electrodes contain metal nitride. For another embodiment, thedielectric layer contains at least one metal oxide dielectric material.For yet another embodiment, the metal oxide buffer layer contains ametal oxide having a composition of the form MO_(x). The metal componentM may be a refractory metal. In one embodiment of the invention, therefractory metal is tungsten (W). In one embodiment, the electrodeadjacent the buffer layer also includes tungsten. In another embodimentof the invention, the dielectric layer is a metal oxide.

[0013] For another embodiment, the invention includes a method offorming a capacitor. The method includes forming a metal oxide bufferlayer adjacent of the electrode layers. In one embodiment, the methodincludes forming a first electrode layer, forming the metal oxide bufferlayer adjacent on the first electrode layer, forming a dielectric layeron the metal oxide buffer layer, and forming a second electrode layer onthe dielectric layer. In one embodiment of the invention, the methodincludes oxidizing the first electrode to form a thin metal oxide bufferlayer. In another embodiment of the invention, the thin buffer layer isannealed to further reduce capacitor leakage. In another embodiment ofthe invention, the anneal temperature of the buffer layer is about 700degrees. In another embodiment, the buffer layer is annealed for aboutone minute.

[0014] Further embodiments of the invention include semiconductorstructures and methods of varying scope, as well as apparatus, devices,modules and systems making use of such semiconductor structures andmethods.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 is an elevation view of a layout of a portion of a memoryarray of a memory device according to the teachings of the presentinvention.

[0016] FIGS. 2A-2I are cross-sectional views of a portion of the memorydevice of FIG. 1 at various processing stages according to the teachingsof the present invention.

[0017]FIG. 3 is a block diagram of an integrated circuit memory device.

[0018]FIG. 4 is an elevation view of a wafer containing semiconductordies.

[0019]FIG. 5 is a block diagram of a circuit module.

[0020]FIG. 6 is a block diagram of a memory module.

[0021]FIG. 7 is a block diagram of a electronic system.

[0022]FIG. 8 is a block diagram of a memory system.

[0023]FIG. 9 is a block diagram of a computer system.

[0024]FIG. 10 is a graph of capacitor leakage versus capacitance forthree different annealing temperatures.

[0025]FIG. 11 is an X-ray diffraction spectra of O₃ annealed WN_(x) atdifferent temperatures.

[0026]FIG. 12 is a graph of the impact of backend annealing in H₂ onperformance of a capacitor according to the present invention.

DESCRIPTION OF THE EMBODIMENTS

[0027] In the following detailed description of the preferredembodiments, reference is made to the accompanying drawings which form apart hereof, and in which is shown by way of illustration specificembodiments in which the inventions may be practiced. These embodimentsare described in sufficient detail to enable those skilled in the art topractice the invention, and it is to be understood that otherembodiments may be utilized and that process, electrical or mechanicalchanges may be made without departing from the scope of the presentinvention. The terms wafer and substrate used in the followingdescription include any base semiconductor structure. Both wafer andsubstrate are to be understood as including silicon-on-sapphire (SOS)technology, silicon-on-insulator (SOI) technology, thin film transistor(TFT) technology, doped and undoped semiconductors, epitaxial layers ofa silicon supported by a base semiconductor structure, as well as othersemiconductor structures known to one skilled in the art. Furthermore,when reference is made to a wafer or substrate in the followingdescription, previous process steps may have been utilized to formregions/junctions on the base semiconductor structure, and terms waferor substrate include the underlying layers containing suchregions/junctions. The following detailed description is, therefore, notto be taken in a limiting sense, and the scope of the present inventionis defined only by the appended claims and equivalents thereof.

[0028] The following description will be illustrated in the context ofsemiconductor container capacitors, and in particular, containercapacitor memory cells for dynamic memory devices. It will be apparentto those skilled in the art that other capacitor structures, e.g.,trench capacitors and parallel plate capacitors, are suitable for usewith the various embodiments of the invention. It will further beapparent to those skilled in the art that the capacitor structuresdescribed herein and their methods of fabrication can be adapted to avariety of integrated circuit devices and applications, some of whichmay be apart from memory devices. Accordingly, the structures of thepresent invention described herein are not limited to the exampleembodiments.

[0029]FIG. 1 depicts the general layout of a portion of a memory arrayof a memory device in accordance with one embodiment of the invention.The memory array includes container capacitor memory cells 200 formedoverlying active areas 208. Active areas 208 are separated by fieldisolation regions 210. Active areas 208 and field isolation regions 210are formed overlying a semiconductor substrate.

[0030] The memory cells 200 are arrayed substantially in rows andcolumns. Shown in FIG. 1 are portions of three rows 201A, 201B and 201C,collectively 201. Separate digit lines (not shown) would be formedoverlying each row 201 and coupled to active areas 208 through digitline contacts 206. Word lines 202 and 204 are further coupled to activeareas 208, with word lines 202 coupled to active areas 208 in row 201Band word lines 204 coupled to active areas 208 in rows 201A and 201C.The word lines 202 and 204, coupled to memory cells in this alternatingfashion, generally define the columns of the memory array. This foldedbit-line architecture is known to one of ordinary skill for permittinghigher densities of memory cells 200 on a substrate.

[0031] FIGS. 2A-2I depict one embodiment of a portion of the processingto fabricate the memory device of FIG. 1. FIGS. 2A-2I arecross-sectional views taken along line A-A′ of FIG. 1 during variousprocessing stages.

[0032] In FIG. 2A, field isolation regions 210 are formed on a substrate205. Substrate 205 may be a silicon substrate, such as a P-type siliconsubstrate. Field isolation regions 210 are generally formed of aninsulator material, such as silicon oxides, silicon nitrides or siliconoxynitrides. For this embodiment, field isolation regions 210 are formedof silicon dioxide such as by conventional local oxidation of silicon(LOCOS) which creates substantially planar regions of oxide on thesubstrate surface. Active areas 208 are those areas not covered by thefield isolation regions 210 on substrate 205. The creation of the fieldisolation regions 210 is preceded or followed by the formation of a gatedielectric layer 212. For this embodiment, gate dielectric layer 212 isa thermally grown silicon dioxide, but may be other insulator materialsdescribed herein or known in the art.

[0033] Following the creation of the field isolation regions 210 andgate dielectric layer 212, a first conductively doped gate polysiliconlayer 216, a gate barrier layer 218, a gate conductor layer 220, a gatecap layer 222 and gate spacers 214 are formed by methods known in theart. Gate barrier layer 218 may be a metal nitride, such as titaniumnitride or tungsten nitride. Gate conductor layer 220 may be anyconductive material, for example a metal. Gate cap layer 222 is oftensilicon nitride while gate spacers 214 are generally of an insulatormaterial such as silicon oxide, silicon nitride and silicon oxynitride.The foregoing layers are patterned to form word lines 202 and 204 asgates for field effect transistors (FET), which FET's are one type ofaccess devices to a data storage unit (capacitor) in a memory cell. Theconstruction of the word lines 202 and 204 are illustrative only. As afurther example, the construction of the word lines 202 and 204 mayinclude a refractory metal silicide layer overlying a polysilicon layer.The metals of chromium (Cr), cobalt (Co), hafnium (Hf), molybdenum (Mo),niobium (Nb), tantalum (Ta), titanium (Ti), tungsten (W), vanadium (V)and zirconium (Zr) are generally recognized as refractory metals. Otherconstructions for word lines 202 and 204 are known to those skilled inthe art.

[0034] Source/drain regions 228 are formed in the substrate 205 such asby conductive doping of the substrate. Source/drain regions have aconductivity opposite the substrate 205. For a P-type substrate,source/drain regions 228 would have an N-type conductivity. Suchconductive doping may be accomplished through ion implantation ofphosphorus or arsenic for this embodiment. As is often the case,source/drain regions 228 include lightly-doped regions 230 created bydifferential levels of ion concentration or even differing dopant ions.Word lines 202 and 204 are adapted to be coupled to periphery contacts(not shown). The periphery contacts are located at the end of the memoryarray and are adapted for electrical communication with externalcircuitry.

[0035] The formation of the word lines 202 and 204 as described are anexample of one application to be used in conjunction with variousembodiments of the invention. Other methods of fabrication and otherapplications are also feasible and perhaps equally viable. For clarityand to focus on the formation of the capacitor structures, many of thereference numbers are eliminated from subsequent drawings, e.g., thosepertaining to the structure of the word lines and the source/drainregions.

[0036] In FIG. 2B, a thick insulating layer 235 is deposited overlyingsubstrate 205, as well as word lines 202 and 204, field isolationregions 210 and active areas 208. Insulating layer 235 is an insulatormaterial such as silicon oxide, silicon nitride and silicon oxynitridematerials. For one embodiment, insulating layer 235 is a doped insulatormaterial such as borophosphosilicate glass (BPSG), a boron andphosphorous-doped silicon oxide. It is understood that other insulatingmaterials known to those of skill in the art may be used. The insulatinglayer 235 is planarized, such as by chemical-mechanical planarization(CMP), in order to provide a uniform height. A mask 237 is formedoverlying insulating layer 235 and patterned to define future locationsof capacitors.

[0037] In FIG. 2C, portions of insulating layer 235 exposed by patternedmask 237 are removed and mask 237 is subsequently removed. The portionsof insulating layer 235 may be removed by etching or other suitableremoval technique known to those skilled in the art. Removal techniquesare generally dependent upon the material of construction of the layerto be removed as well as the surrounding layers to be retained.Patterning of insulating layer 235 creates openings having bottomportions 236A overlying exposed portions of the substrate 205 andsidewalls 236B defined by the insulating layer 235.

[0038] In FIG. 2D, a layer of doped polysilicon is formed overlyingexposed portions of active area 208 and top portions of insulating layer235 to form contact layer 240. Contact layer 240 may be formed bycontrolled deposition of polysilicon as shown in FIG. 2D. Alternatively,contact layer 240 may be blanket deposited polysilicon followed by anetch-back to leave a layer of polysilicon overlying exposed portions ofactive area 208 between word lines 202 and 204. For still furtherembodiments, contact layer 240 is formed from tungsten, titaniumnitride, tungsten nitrides, tantalum nitride, aluminum or otherconductive materials, metals or alloys.

[0039] In FIG. 2E, the portions of contact layer 240 overlyinginsulating layer 235 are removed leaving contacts 240 between the wordlines 202 and 204. A bottom electrode 245 is formed overlying thecontacts 240 and insulating layer 235. Bottom electrode 245 is anyconductive material. For one embodiment, bottom electrode 245 contains ametal nitride. For another embodiment, the metal component of the bottomelectrode 245 is a refractory metal, resulting in a refractory metalnitride. For yet another embodiment, bottom electrode 245 containstungsten nitride (WN_(n); 0<n<=6).

[0040] Bottom electrode 245 may be formed by any method, such ascollimated sputtering, chemical vapor deposition (CVD) or otherdeposition techniques. In the case of a metal nitride material, bottomelectrode 245 may be deposited as a metal layer followed by nitridation.

[0041] Bottom electrode 245 forms the bottom conductive layer orelectrode of the capacitor. For one embodiment, the bottom conductivelayer has a closed bottom and sidewalls extending up from the closedbottom as shown in FIG. 2E. For another embodiment, the bottomconductive layer has a substantially planar surface as in a parallelplate capacitor. Bottom electrode 245 may contain more than oneconductive layer, e.g., a metal nitride layer overlying a metal silicidelayer. Subsequent annealing of the memory device may produce a reactionbetween bottom electrode 245 and contact 240 such that an interfacelayer is formed. As an example, where bottom electrode 245 contains arefractory metal or refractory metal nitride, and contact 240 containspolysilicon, subsequent annealing can produce a refractory metalsilicide interface between bottom electrode 245 and contact 240. Suchmetal silicide interface layers are often advantageous in reducingelectrical resistance to contact 240.

[0042] In FIG. 2F, a buffer layer 250 is formed overlying bottomelectrode 245. The buffer layer 250 is shown to be directly adjoiningbottom electrode 245. But buffer layer 250 is not shown to scalerelative to bottom electrode 245 for convenience and clarity ofillustration. Buffer layer 250 is a metal oxide material having acomposition of the form MO_(x). In one embodiment, the metal component Mis a refractory metal. The refractory metals of chromium (Cr), cobalt(Co), hafnium (Hf), molybdenum (Mo), niobium (Nb), tantalum (Ta),titanium (Ti), tungsten (W), vanadium (V) and zirconium (Zr) areincluded in this definition. For one embodiment, buffer layer 250contains a tungsten oxide material (WO_(x)). Metal oxide buffer layerscan act to reduce capacitor leakage.

[0043] Benefits may be derived by matching the metal oxide buffer layerto the adjacent metal nitride electrode. For example, the WO_(x) bufferlayer 250 can be grown by oxidizing the WN_(x) bottom electrode layer245. Accordingly, the metal component of the metal oxide buffer layer250 and the metal component of the metal nitride of bottom electrode 245are both tungsten. Such matching of the buffer layer to the electrodecan be utilized to reduce stress between the two layers, thus improvingdevice reliability. Furthermore, such matching allows formation ofbottom electrode 245 and buffer layer 250 using a single depositionprocess along with an oxidation process.

[0044] For one embodiment, buffer layer 250 is formed from the bottomelectrode 245 containing metal nitride. For this embodiment, the metalnitride of the bottom electrode 245 is oxidized to form the metal oxide.Such oxidation may use a variety of techniques including oxidation in anambient containing O₂ or ozone (O₃), with or without the help of plasma,or UV light or remote plasma. Controlled oxidation of the metal nitridecan be used to form the metal oxide buffer layer 250, at the upper,exposed surface of bottom electrode 245. For a further embodiment,buffer layer 250 is grown by oxidizing a WN_(x) bottom electrode 245 inan oxygen-containing ambient thereby using tungsten at the surface ofthe bottom electrode to grow a WO₃ buffer layer. In one embodiment, thebuffer layer 250 is grown in an O₂ or O₃ ambient at a temperature in therange of 300 to 550 degrees Celsius. The buffer layer 250 may be grownwith or without a plasma in the environment. The bottom electrode 245now includes W₂N film adjacent the WO₃ buffer layer 250 due to theoxidation process.

[0045] In one embodiment, buffer layer 250, bottom electrode 245 andsubstrate are annealed at a temperature of at least 700 degrees Celsiusin an inert gas ambient. The inert gases include, but are not limitedto, N₂, Ar, or He. The buffer layer is believed to have an orthorhomiccrystalline structure due to the high temperature anneal.

[0046] In FIG. 2G, a dielectric layer 255 is formed overlying bufferlayer 250. The dielectric layer 255 is shown to be adjoining bufferlayer 250, but there is no prohibition to forming additional layersinterposed between dielectric layer 255 and buffer layer 250 as same maybe suitable in some applications of the present invention. Note,however, that the nature of any additional layer may adversely affectperformance of the resulting capacitor such as creating an undesirableseries capacitance.

[0047] Dielectric layer 255 contains a dielectric material. For oneembodiment, dielectric layer 255 contains at least one metal oxidedielectric material. For another embodiment, dielectric layer 255contains a Tantalum Oxide, such as Ta₂O₅. Dielectric layer 255 may bedeposited by any deposition technique, e.g., RF-magnetron sputtering,chemical vapor deposition (CVD). As one example, a metal oxide, e.g.,tantalum oxide, may be formed by depositing a layer of the metalcomponent, e.g., tantalum, followed by annealing in an oxygen-containingambient. As another example, the metal oxide may be deposited by metalorganic chemical vapor deposition (MOCVD). Subsequent to formation,dielectric layer 255 may be annealed in an oxygen-containing ambient,such as an ambient containing O₂ or ozone, at a temperature within therange of approximately 200 to 800° C. The actual oxygen-containingambient, concentration of oxygen species and annealing temperature mayvary for the specific dielectric deposited. These variations are knownto those skilled in the art.

[0048] Bottom electrode 245 is generally not oxidized, or is onlymarginally oxidized, during formation or subsequent processing ofdielectric layer 255 due to the protection from the oxygen-containingambient and diffusion of oxygen as provided by buffer layer 250.However, insulators generally create a series capacitance of the bufferlayer and the dielectric layer. Such series capacitance candetrimentally impact the overall capacitance of the capacitor structurewhen the insulative buffer layer has a dielectric constant less thanthat of the dielectric layer. Accordingly, the buffer layer has adielectric constant greater than the dielectric constant of thedielectric layer. For example, the WO₃ buffer layer has a dielectricconstant of about 300 and a Ta₂O₅ dielectric layer has a dielectricconstant of about 20-25. Accordingly, the dielectric layer determinesthe capacitance with little detrimental effect, e.g. series capacitance,by the buffer layer.

[0049] In FIG. 2H, a top electrode 265 is deposited to form the topconductive layer or electrode of the capacitor. The top electrode 265 isshown to be directly adjoining dielectric layer 255, but there is noprohibition to forming additional conductive layers interposed betweenthe top electrode 265 and dielectric layer 255. Top electrode 265 may beof any conductive material and generally follows the same guidelines asbottom electrode 245. For one embodiment, top electrode 265 containsPt—Rh deposited by CVD. Layers 245 through 270 are then patterned bytechniques known in the art to define capacitors of memory cells 200 inFIG. 21.

[0050] In addition, the figures were used to aid the understanding ofthe accompanying text. However, the figures are not drawn to scale andrelative sizing of individual features and layers are not necessarilyindicative of the relative dimensions of such individual features orlayers in application. As an example, while bottom electrode 245 isdrawn to have an illustrated thickness of approximately the same asdielectric layer 255, for purposes of clarity and convenience, bottomelectrode 245 may have a physical thickness of five times that ofdielectric layer 255 in some applications. In one embodiment, bottomelectrode 245 has a thickness of about 200-400 Å. In one embodiment, thebuffer layer has a thickness of about 50-150 Å. In one embodiment, thedielectric layer 255 has a thickness of about 60-100 Å. In oneembodiment, the top electrode 265 has a thickness of about 200-800 Å.One of ordinary skill in the art will understand upon reading thedisclosure the suitable thicknesses of such layers for carrying out thepresent invention. Accordingly, the drawings are not to be used fordimensional characterization.

[0051] While the foregoing embodiments of capacitor structures may beused in a variety of integrated circuit devices, they are particularlysuited for use as storage capacitors of memory cells found in dynamicmemory devices.

[0052] Memory Devices

[0053]FIG. 3 is a simplified block diagram of a memory device accordingto one embodiment of the invention. The memory device 300 includes anarray of memory cells 302, address decoder 304, row access circuitry306, column access circuitry 308, control circuitry 310, andInput/Output circuit 312. The memory can be coupled to an externalmicroprocessor 314, or memory controller for memory accessing. Thememory receives control signals from the processor 314, such as WE*,RAS* and CAS* signals. The memory is used to store data which isaccessed via I/O lines. It will be appreciated by those skilled in theart that additional circuitry and control signals can be provided, andthat the memory device of FIG. 3 has been simplified to help focus onthe invention. At least one of the memory cells or associated circuitryhas a capacitor in accordance with the present invention.

[0054] It will be understood that the above description of a DRAM(Dynamic Random Access Memory) is intended to provide a generalunderstanding of the memory and is not a complete description of all theelements and features of a DRAM. Further, the invention is equallyapplicable to any size and type of memory circuit and is not intended tobe limited to the DRAM described above. Other alternative types ofdevices include SRAM (Static Random Access Memory) or Flash memories.Additionally, the DRAM could be a synchronous DRAM commonly referred toas SGRAM (Synchronous Graphics Random Access Memory), SDRAM (SynchronousDynamic Random Access Memory), SDRAM II, and DDR SDRAM (Double Data RateSDRAM), as well as Synchlink or Rambus DRAMs and other emerging DRAMtechnologies.

[0055] As recognized by those skilled in the art, memory devices of thetype described herein are generally fabricated as an integrated circuitcontaining a variety of semiconductor devices. The integrated circuit issupported by a substrate. Integrated circuits are typically repeatedmultiple times on each substrate. The substrate is further processed toseparate the integrated circuits into dies as is known in the art.

[0056] Semiconductor Dies

[0057] With reference to FIG. 4, for one embodiment, a semiconductor die410 is produced from a wafer 400. A die is an individual pattern,typically rectangular, on a substrate that contains circuitry, orintegrated circuit devices, to perform a specific function. Asemiconductor wafer will typically contain a repeated pattern of suchdies containing the same functionality. Die 410 may contain circuitryfor the inventive memory device, as discussed above. Die 410 may furthercontain additional circuitry to extend to such complex devices as amonolithic processor with multiple functionality. Die 410 is typicallypackaged in a protective casing (not shown) with leads extendingtherefrom (not shown) providing access to the circuitry of the die forunilateral or bilateral communication and control. Each die 410 maycontain at least one of the capacitors according to the presentinvention.

[0058] Circuit Modules

[0059] As shown in FIG. 5, two or more dies 410 may be combined, with orwithout protective casing, into a circuit module 500 to enhance orextend the functionality of an individual die 410. Circuit module 500may be a combination of dies 410 representing a variety of functions, ora combination of dies 410 containing the same functionality. One or moredies 410 of circuit module 500 contain at least one capacitor inaccordance with the invention.

[0060] Some examples of a circuit module include memory modules, devicedrivers, power modules, communication modems, processor modules andapplication-specific modules, and may include multilayer, multichipmodules. Circuit module 500 may be a subcomponent of a variety ofelectronic systems, such as a clock, a television, a cell phone, apersonal computer, an automobile, an industrial control system, anaircraft and others. Circuit module 500 will have a variety of leads 410extending therefrom and coupled to the dies 410 providing unilateral orbilateral communication and control.

[0061]FIG. 6 shows one embodiment of a circuit module as memory module600. Memory module 600 contains multiple memory devices 610 contained onsupport 615, the number generally depending upon the desired bus widthand the desire for parity. Memory module 600 accepts a command signalfrom an external controller (not shown) on a command link 620 andprovides for data input and data output on data links 630. The commandlink 620 and data links 630 are connected to leads 640 extending fromthe support 615. Leads 640 are shown for conceptual purposes and are notlimited to the positions shown in FIG. 6. At least one of the memorydevices 610 contains a capacitor according to the present invention.

[0062] Electronic Systems

[0063]FIG. 7 shows one embodiment of an electronic system 700 containingone or more circuit modules 500. Electronic system 700 generallycontains a user interface 710. User interface 710 provides a user of theelectronic system 700 with some form of control or observation of theresults of the electronic system 700. Some examples of user interface710 include the keyboard, pointing device, monitor or printer of apersonal computer; the tuning dial, display or speakers of a radio; theignition switch, gauges or gas pedal of an automobile; and the cardreader, keypad, display or currency dispenser of an automated tellermachine. User interface 710 may further describe access ports providedto electronic system 700. Access ports are used to connect an electronicsystem to the more tangible user interface components previouslyexemplified. One or more of the circuit modules 500 may be a processorproviding some form of manipulation, control or direction of inputs fromor outputs to user interface 710, or of other information eitherpreprogrammed into, or otherwise provided to, electronic system 700. Aswill be apparent from the lists of examples previously given, electronicsystem 700 will often be associated with certain mechanical components(not shown) in addition to circuit modules 500 and user interface 710.It will be appreciated that the one or more circuit modules 500 inelectronic system 700 can be replaced by a single integrated circuit.Furthermore, electronic system 700 may be a subcomponent of a largerelectronic system. It will also be appreciated that at least one of thememory modules 500 contains a capacitor according to the presentinvention.

[0064]FIG. 8 shows one embodiment of an electronic system as memorysystem 800. Memory system 800 contains one or more memory modules 600and a memory controller 810. The memory modules 600 each contain one ormore memory devices 610. At least one of memory devices 610 contain acapacitor according to the present invention. Memory controller 810provides and controls a bidirectional interface between memory system800 and an external system bus 820. Memory system 800 accepts a commandsignal from the external bus 820 and relays it to the one or more memorymodules 600 on a command link 830. Memory system 800 provides for datainput and data output between the one or more memory modules 600 andexternal system bus 820 on data links 840. It will also be appreciatedthat at least one of the memory modules 600 contains a capacitoraccording to the present invention.

[0065]FIG. 9 shows a further embodiment of an electronic system as acomputer system 900. Computer system 900 contains a processor 910 and amemory system 800 housed in a computer unit 905. Computer system 900 isbut one example of an electronic system containing another electronicsystem, i.e., memory system 800, as a subcomponent. Computer system 900optionally contains user interface components. Depicted in FIG. 9 are akeyboard 1220, a pointing device 930, a monitor 940, a printer 950 and abulk storage device 960. It will be appreciated that other componentsare often associated with computer system 900 such as modems, devicedriver cards, additional storage devices, etc. It will further beappreciated that the processor 910 and memory system 800 of computersystem 900 can be incorporated on a single integrated circuit. Suchsingle package processing units reduce the communication time betweenthe processor and the memory circuit. It will be appreciated that atleast one of the processor 910 and memory system 800 contain a capacitoraccording to the present invention.

[0066] Test results

[0067] FIGS. 10-12 show results from various test wafers. The testwafers all include a deep container, high-k MIM capacitor formed of aWN_(x) bottom electrode deposited by CVD on a substrate, an 80 Å Ta₂O₅dielectric layer deposited by CVD, and a Pt—Rh alloy top electrode alsodeposited by CVD. A buffer layer is formed by oxidizing the WN_(x)bottom electrode prior to depositing the dielectric layer. The testwafers were oxidized in an O₃ ambient at 475 degrees Celsius for threeminutes. The buffer layer comprises a WO₃ layer and the bottom electrodeincludes a W₂N layer adjacent the buffer layer. After creation of theWO₃ buffer layer and before depositing the dielectric layer, the bufferlayer/bottom electrode stack is annealed in an N₂ ambient for one minuteat various temperatures ranging from 500 to 700 degrees Celsius. Thedielectric layer is deposited at 475 degrees Celsius in an O₂ ambient.The Pt—Rh alloy top electrode is deposited according to techniques knownto those of skill in the art.

[0068]FIG. 10 shows capacitance and leakage measurements from threewafers having a plurality of MIM container capacitors. All capacitorswere created according to the above method with the WO₃ buffer layersand adjacent electrodes on each wafer being annealed at varioustemperatures. Test capacitors 1 (denoted as Δ) were created by annealingthe WO₃ buffer layer/electrode stack at a temperature of 500 degreesCelsius. Test capacitors 2 (denoted as □) were created by annealing theWO₃ buffer layer/electrode stack at a temperature of 600 degreesCelsius. Test capacitors 3 (denoted as ♦) were created by annealing theWO₃ buffer layer/electrode stack at a temperature of 700 degreesCelsius. As evident from the plotted data points representing leakageand capacitance, the higher temperature anneal represented by the testcapacitors 3 (denoted as ♦) yields higher capacitance and lower leakagerelative to the lower temperature anneal represented by test capacitors1 and 2 (respectively denoted by Δ and □).

[0069]FIG. 11 shows an X-ray diffraction spectra of two WO₃ buffer layersamples. The lighter line represents a first sample which was annealedat a temperature of 650 degrees Celsius. The darker data line representsa second sample which was annealed at a temperature of 700 degreesCelsius. Both stacks were annealed in an N₂ ambient for one minute. Thegraph further indicates the peaks of the W₂N layer of the bottom,adjacent electrode. It is noted that the peaks of the W₂N layer samplesdo not shift for the two annealing temperatures. The spectra shows thatthe WO₃ peaks of the 700 degree annealed, second stack shift toward alower 2-theta angle than the WO₃ peaks of the 650 degree annealed, firststack. The shift was about 0.5 to 1 degree. As a result, it isidentified that the 700 degree annealed buffer layer has an orthorhomiccrystal structure, while the 650 degree annealed buffer layer has amonoclinic crystal structure. Orthorhomic structures are more stable athigher temperatures than monoclinic structures.

[0070] Shifts in 2-theta angle can at times be attributed to filmstress. However, the shift shown in FIG. 11 is believed to not be causedby film stress as the W₂N peaks did not shift as a function of thedifferent anneal temperatures.

[0071] In one embodiment, the anneal temperature of the bufferlayer/electrode stack is about 700 degrees Celsius. As discussed inconjunction with the test results, a higher anneal temperature of thebuffer layer yields a capacitor with higher capacitance and lowerleakage. It is believed that the high temperature anneal (at about, orgreater than, 700 degrees Celsius) changes the phase of the WO₃ latticestructure from a monoclinic crystalline structure to an orthorhomiccrystalline structure, which is more stable than monoclinic latticestructures at higher temperatures.

[0072]FIG. 12 graphically shows the effect of backend wafer processingon capacitor leakage. Integrated circuits that include transistors aresometimes subjected to backend processing which improves the reliabilityof the structures. Backend processing typically includes annealing thewafer in a hydrogen ambient, for example in an ambient of 10% hydrogenand 90% nitrogen. Such backend processing results in a more robustinterface for the transistors. The sets of capacitors denoted by ♦, +,and ◯ were not subjected to backend processing. The sets of capacitorsdenoted by □, Δ, and  were respectively fabricated in the same manneras sets of capacitors ⋄, +, and ◯ and then were subject to backendprocessing. All of the capacitors ⋄, +, ◯, □, Δ, and  have a structureas shown in FIG. 2I. The sets of capacitors denoted by ◯ and  had theirbottom electrodes and buffer layers annealed at 750 degrees Celsius. Thesets of capacitors denoted by + and Δ had their bottom electrodes andbuffer layers annealed at 550 degrees Celsius. The sets of capacitorsdenoted by ⋄ and □ did not anneal their bottom electrodes and bufferlayers.

[0073] As shown in the graph of FIG. 12, the leakage of the capacitorswhich were not subject to backend processing is less than thosecapacitors which were subject to backend processing. But annealing thebottom electrode and buffer layer did reduce the leakage compared to notannealing. More specifically, the median leakage of capacitors, whichwere annealed at 750 degrees Celsius, is about 70 fA. Whereas the medianleakages for capacitors Δ and capacitors □, which were respectivelyannealed at 550 degrees Celsius and not annealed, are about 100 fA and200 fA, respectively. Accordingly, the high temperature anneal of thebuffer layer 250 and bottom electrode 245 resulted in capacitors whichhave less leakage than those annealed at lower temperatures or notannealed. It is believed that the capacitors which are subjected to thehigh temperature anneal (greater than 700 degrees Celsius, and in oneembodiment at about 750 degrees Celsius) are more stable and thus lesseffected by the backend hydrogen anneal processing.

[0074] The other capacitors (denoted by ⋄, +, and ◯) not subject tobackend processing have a leakage which is less than the leakage of thecapacitors subjected to backend processing. While not visible on thescale of FIG. 12, these capacitors follow the above findings that thecapacitor with a buffer layer according to the present invention whichis subject to a high temperature anneal has less leakage than thecapacitors which were not subject to a high temperature anneal.

[0075] It is foreseen that the present invention can be practiced withor without the backend processing. For example, it is possible to createthe transistors on a wafer and then subject same to backend processingprior to creating the capacitors according to the present invention,e.g. capacitor over digit line structures.

[0076] While the invention has been described and illustrated withrespect to forming container capacitors for a memory cell, it should beapparent that substantially similar processing techniques can be used toform other container capacitors for other applications as well as othercapacitor structures. As one example, capacitors formed in accordancewith the methods described herein may be used as on-chip capacitorsutilized to reduce lead impedance of a packaged integrated circuit chip.As further example, parallel plate or trench capacitors may be formedwith a metal oxide barrier layer between a dielectric layer and anelectrode.

[0077] Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement which is calculated to achieve the same purpose maybe substituted for the specific embodiments shown. Many adaptations ofthe invention will be apparent to those of ordinary skill in the art.For example, other materials and shapes, as well as other deposition andremoval processes, may be utilized in conjunction with the invention.Accordingly, this application is intended to cover any adaptations orvariations of the invention. It is manifestly intended that thisinvention be limited only by the following claims and equivalentsthereof.

CONCLUSION

[0078] Capacitor structures and methods of their manufacture have beendescribed for use in integrated circuits. The capacitor structuresinclude two electrodes and a dielectric layer interposed between the twoelectrodes. The capacitor structures further include a metal oxidebuffer layer interposed between the dielectric layer and one of theelectrodes. The metal oxide buffer layer acts to reduce leakage andyield higher capacitance. The capacitors are suited for use in memorycells and apparatus incorporating such memory cells, as well as in otherintegrated circuits.

What is claimed is:
 1. A capacitor, comprising: a first electrode; asecond electrode; a dielectric layer interposed between the firstelectrode and the second electrode; and a metal oxide buffer layerintermediate the dielectric layer and one of the first and secondelectrodes.
 2. The capacitor according to claim 1, wherein the oneelectrode is a tungsten nitride and the buffer layer is a tungstenoxide.
 3. The capacitor according to claim 2, wherein the dielectriclayer is a tantalum oxide.
 4. The capacitor according to claim 1,wherein the buffer layer has a orthorhomic crystalline structure.
 5. Acapacitor, comprising: a first electrode; a second electrode; adielectric layer interposed between the first electrode and the secondelectrode; and a tungsten trioxide buffer layer interposed between thedielectric layer and one of the first and second electrodes.
 6. Thecapacitor according to claim 5, wherein the buffer layer has aorthorhomic crystalline structure.
 7. The capacitor according to claim5, wherein the one electrode includes tungsten.
 8. The capacitoraccording to claim 7, wherein the buffer layer is grown by oxidizing theone electrode.
 9. A capacitor, comprising: a first electrode; a secondelectrode; a dielectric layer interposed between the first electrode andthe second electrode; and a metal oxide buffer layer interposed betweenthe dielectric layer and one of the first and second electrodes, whereinthe metal oxide buffer layer includes a refractory metal.
 10. Thecapacitor according to claim 9, wherein the buffer layer is of theformula MO_(x), and M is a metal component from a group consisting oftungsten, tantalum, zirconium, and hafnium.
 11. The capacitor accordingto claim 9, wherein the buffer layer has a orthorhomic crystallinestructure.
 12. A vertical capacitor, comprising: a bottom electrode; atop electrode positioned above the bottom electrode; a dielectric layerinterposed between the top electrode and the bottom electrode; and ametal oxide buffer layer intermediate the dielectric layer and thebottom electrode.
 13. The capacitor according to claim 12, wherein thebottom electrode is a tungsten nitride and the buffer layer is atungsten oxide.
 14. The capacitor according to claim 13, wherein thedielectric layer is a tantalum oxide.
 15. The capacitor according toclaim 12, wherein the buffer layer has a orthorhomic crystallinestructure.
 16. A capacitor, comprising: a bottom electrode; a topelectrode; a dielectric layer interposed between the top electrode andthe bottom electrode; and a metal oxide buffer layer intermediate thedielectric layer and the bottom electrode, wherein the metal in thebuffer layer is a refractory metal.
 17. The capacitor according to claim16, wherein the metal in the buffer layer is tungsten.
 18. The capacitoraccording to claim 17, wherein the bottom electrode comprises a metalnitride, and the metal in the bottom electrode is a refractory metal.19. The capacitor according to claim 18, wherein the bottom electrodecomprises tungsten nitride.
 20. A capacitor, comprising: a bottomelectrode; a top electrode; a dielectric layer interposed between thetop electrode and the bottom electrode; and a metal oxide buffer layerintermediate the dielectric layer and the bottom electrode, wherein thebottom electrode comprises a metal nitride having a metal componentwhich is the same as the metal component of the metal oxide bufferlayer.
 21. The capacitor according to claim 20, wherein the dielectriclayer comprises tantalum oxide.
 22. The capacitor according to claim 21,wherein the metal component of the bottom electrode and the buffer layerincludes tungsten.
 23. A capacitor, comprising: a bottom electrode; atop electrode; a dielectric layer interposed between the bottomelectrode and the top electrode; and at least one tungsten oxide bufferlayer, wherein each tungsten oxide buffer layer is interposed betweenthe dielectric layer and an electrode selected from the group consistingof the bottom electrode and the top electrode; wherein at least oneelectrode selected from the group consisting of the bottom electrode andthe top electrode comprises tungsten nitride.
 24. The capacitoraccording to claim 23, wherein the dielectric layer is a metal oxide ofa different type than the buffer layer.
 25. A capacitor, comprising: afirst electrode; a second electrode; a tantalum oxide dielectric layerinterposed between the bottom electrode and the top electrode; and atleast one tungsten oxide buffer layer, wherein each tungsten oxidebuffer layer is interposed between the dielectric layer and an electrodeselected from the group consisting of the bottom electrode and the topelectrode; wherein at least one electrode is selected from the groupconsisting of the bottom electrode and the top electrode includestungsten nitride.
 26. A capacitor, comprising: a first electrode; asecond electrode; a dielectric layer interposed between the firstelectrode and the second electrode; and a metal oxide buffer layerintermediate the dielectric layer and one of the first and secondelectrodes, wherein the metal oxide buffer layer has an orthorhomiccrystal structure.
 27. The capacitor according to claim 26, wherein themetal in the buffer layer is tungsten.
 28. A capacitor, comprising: abottom electrode; a top electrode; a dielectric layer interposed betweenthe top electrode and the bottom electrode; and an annealed metal oxidebuffer layer intermediate the dielectric layer and the bottom electrode.29. The capacitor according to claim 28, wherein the bottom electrodecomprises a metal nitride and has a metal component which is the same asthe metal component of the metal oxide buffer layer.
 30. A capacitor,comprising: a first electrode; a second electrode; a dielectric layerinterposed between the first electrode and the second electrode; and ametal oxide buffer layer intermediate the dielectric layer and one ofthe first and second electrodes; wherein the buffer layer has adielectric constant greater than the dielectric layer.
 31. The capacitoraccording to claim 30, wherein the one of the first and secondelectrodes has a metal component which is the same as the metalcomponent of the buffer layer.
 32. The capacitor according to claim 30,wherein the buffer layer has an orthorhomic crystalline structure.
 33. Amethod of forming a capacitor, comprising: forming a bottom electrodelayer; forming a metal oxide buffer layer overlying the bottom electrodelayer; forming a dielectric layer overlying the metal oxide bufferlayer; and forming a top electrode layer overlying the dielectric layer.34. The method of claim 33, further comprising patterning the topelectrode layer, the buffer layer, the dielectric layer, and the bottomelectrode layer to define the capacitor.
 35. The method of claim 33,wherein the method is performed in the order presented.
 36. A method offorming a capacitor, comprising: forming a bottom electrode layer;forming a metal oxide buffer layer overlying the bottom electrode layer;annealing the buffer layer; forming a dielectric layer overlying themetal oxide buffer layer; and forming a top electrode layer overlyingthe dielectric layer.
 37. The method of claim 36, further comprisingpatterning the top electrode layer, the buffer layer, the dielectriclayer, and the bottom electrode layer to define the capacitor.
 38. Themethod of claim 36, wherein the method is performed in the orderpresented.
 39. A method of forming a capacitor, comprising: forming abottom electrode layer on a substrate; oxidizing the bottom electrodelayer to form a metal oxide buffer layer overlying the bottom electrodelayer; forming a dielectric layer overlying the metal oxide bufferlayer; and forming a top electrode layer overlying the dielectric layer.40. The method of claim 39, wherein the method is performed in the orderpresented.
 41. A method of forming a capacitor, comprising: forming abottom electrode layer on a substrate; oxidizing the bottom electrodelayer to form a metal oxide buffer layer overlying the bottom electrodelayer; annealing the buffer layer; forming a dielectric layer overlyingthe metal oxide buffer layer; and forming a top electrode layeroverlying the dielectric layer.
 42. The method of claim 41, wherein themethod is performed in the order presented.
 43. The method of claim 42,wherein the bottom electrode is deposited by chemical vapor deposition,and the top electrode is deposited by chemical vapor deposition.
 44. Themethod of claim 41, wherein the dielectric layer is formed to athickness of about 80 Å.
 45. A method of forming a capacitor,comprising: forming a bottom electrode layer on a substrate; oxidizingthe bottom electrode layer to form a metal oxide buffer layer overlyingthe bottom electrode layer; annealing the buffer layer at about 700degrees Celsius; forming a dielectric layer overlying the metal oxidebuffer layer; and forming a top electrode layer overlying the dielectriclayer.
 46. The method of claim 45, wherein the buffer layer is annealedfor about one minute.
 47. The method of claim 45, wherein the bufferlayer is annealed in an N₂ ambient.
 48. A method of forming a capacitor,comprising: forming a first electrode layer; forming a second electrodelayer; forming a dielectric layer interposed between the first electrodelayer and the second electrode layer; and forming a metal oxide bufferlayer intermediate the dielectric layer and one of the first and secondelectrode layers.
 49. The method of claim 48, wherein forming the bufferlayer includes oxidizing the one of the first and second electrodelayers to form the buffer layer and thereafter high temperatureannealing the buffer layer.
 50. A method of forming a capacitor,comprising: forming an insulating layer on a substrate; forming anopening in the insulating layer, wherein the opening has a bottomportion overlying an exposed portion of the substrate and sidewallportions defined by the insulating layer; forming a bottom electrodelayer overlying the insulating layer, the exposed portion of thesubstrate and the sidewall portions; forming a metal oxide buffer layeroverlying the bottom electrode layer; forming a dielectric layeroverlying the metal oxide buffer layer; forming a top electrode layeroverlying the dielectric layer; and patterning the top electrode layer,dielectric layer, metal oxide buffer layer and bottom electrode layer tothereby define the capacitor.
 51. The method of claim 50, whereinforming the bottom electrode layer comprises forming a layer of metalnitride.
 52. The method of claim 51, wherein forming the bottomelectrode layer comprises forming a layer of tungsten nitride.
 53. Themethod of claim 52, wherein forming the metal oxide buffer layercomprises oxidizing the bottom electrode layer to form the metal oxidebuffer layer, and annealing the metal oxide buffer layer.
 54. The methodof claim 50, wherein the metal oxide buffer layer is annealed at atemperature of over 650 degrees Celsius.
 55. The method of claim 50,wherein the metal oxide buffer layer is annealed at a temperature of atleast 700 degrees Celsius.
 56. A method of forming a capacitor,comprising: forming an insulating layer on a substrate; forming anopening in the insulating layer, wherein the opening has a bottomportion overlying an exposed portion of the substrate and sidewallportions defined by the insulating layer; forming a tungsten nitridebottom electrode layer overlying the insulating layer, the exposedportion of the substrate and the sidewall portions; forming a tungstenoxide buffer layer overlying the bottom electrode layer; forming adielectric layer overlying the metal oxide buffer layer; forming a topelectrode layer overlying the dielectric layer; and patterning the topelectrode layer, dielectric layer, buffer layer and bottom electrodelayer to thereby define the capacitor.
 57. A method of forming acapacitor, comprising: forming an insulating layer on a substrate;forming an opening in the insulating layer, wherein the opening has abottom portion overlying an exposed portion of the substrate andsidewall portions defined by the insulating layer; forming a tungstennitride bottom electrode layer overlying the insulating layer, theexposed portion of the substrate and the sidewall portions; oxidizingthe bottom electrode layer to form a tungsten oxide buffer layeroverlying the bottom electrode layer; annealing the buffer layer to anorthorhomic crystal lattice; forming a dielectric layer overlying thebuffer layer; forming a top electrode layer overlying the dielectriclayer; and patterning the top electrode layer, dielectric layer, bufferlayer and bottom electrode layer to thereby define the capacitor. 58.The method according to claim 57, wherein annealing the buffer layerincludes annealing at a temperature of at least 700 degrees Celsius. 59.A method of forming a capacitor, comprising: forming an insulating layeron a substrate; forming an opening in the insulating layer, wherein theopening has a bottom portion overlying an exposed portion of thesubstrate and sidewall portions defined by the insulating layer;depositing a tungsten nitride bottom electrode layer overlying theinsulating layer, the exposed portion of the substrate and the sidewallportions; oxidizing the bottom electrode layer to form a tungsten oxidebuffer layer overlying the bottom electrode layer; annealing the bufferlayer at a temperature of at least 700 degrees Celsius to have anorthorhomic crystal lattice; depositing a tantalum oxide dielectriclayer overlying the buffer layer; depositing a metal top electrode layeroverlying the dielectric layer; and patterning the top electrode layer,dielectric layer, buffer layer and bottom electrode layer to therebydefine the capacitor.
 60. The method of claim 59, wherein the metal topelectrode includes a noble metal.
 61. The method of claim 60, whereinthe top electrode includes a platinum alloy.
 62. A method of forming acapacitor, comprising: forming a bottom electrode layer; forming aorthorhomic crystal structured buffer layer overlying the bottomelectrode layer; forming a dielectric layer overlying the buffer layer;and forming a top electrode layer overlying the dielectric layer. 63.The method of claim 62, further comprising patterning the top electrodelayer, the buffer layer, the dielectric layer, and the bottom electrodelayer to define the capacitor.
 64. The method of claim 62, wherein themethod is performed in the order presented.
 65. A method of forming acapacitor, comprising: forming a first electrode layer, wherein thefirst electrode layer comprises a metal nitride having a metalcomponent; forming a buffer layer overlying the first electrode layer,wherein the buffer layer comprises a metal oxide having a composition ofthe form MO_(x), wherein M is a metal component selected from the groupconsisting of chromium, cobalt, hafnium, iridium, molybdenum, niobium,osmium, rhenium, rhodium, ruthenium, tantalum, titanium, tungsten,vanadium and zirconium; forming a dielectric layer overlying the bufferlayer; forming a second electrode layer overlying the buffer layer,wherein the second electrode layer comprises a metal nitride having ametal component; and patterning the second electrode layer, dielectriclayer, buffer layer and first electrode layer to thereby define thecapacitor.
 66. The method of claim 65, wherein the metal component ofthe first electrode layer is tungsten.
 67. The method of claim 67,wherein the metal component M of the buffer layer is selected to be thesame as the metal component of the first electrode layer.
 68. The methodof claim 66, wherein the dielectric layer comprises a metal oxidedielectric material.
 69. The method of claim 66, wherein the method isperformed in the order presented.
 70. A method of forming a capacitor,comprising: forming a bottom electrode layer; forming a metal oxidebuffer layer overlying the bottom electrode layer; forming a dielectriclayer having a dielectric constant less than the buffer overlying thebuffer layer; and forming a top electrode layer overlying the dielectriclayer.
 71. The method of claim 70, further comprising patterning the topelectrode layer, the buffer layer, the dielectric layer, and the bottomelectrode layer to define the capacitor.
 72. The method of claim 70,wherein the method is performed in the order presented.
 73. Asemiconductor die, comprising: an integrated circuit supported by asubstrate and having a plurality of integrated circuit devices, whereinat least one of the plurality of integrated circuit devices comprises acapacitor, the capacitor comprising: a first electrode; a secondelectrode; a dielectric layer interposed between the first electrode andthe second electrode; and at least one metal oxide buffer layerinterposed between the dielectric layer and an electrode selected fromthe group consisting of the first electrode and the second electrode.74. A semiconductor die, comprising: an integrated circuit supported bya substrate and having a plurality of integrated circuit devices,wherein at least one of the plurality of integrated circuit devicescomprises a capacitor, the capacitor comprising: a first electrode; asecond electrode; a dielectric layer interposed between the firstelectrode and the second electrode; and at least one tungsten oxidebuffer layer, wherein each tungsten oxide buffer layer is interposedbetween the dielectric layer and an electrode selected from the groupconsisting of the first electrode and the second electrode.
 75. Asemiconductor die, comprising: an integrated circuit supported by asubstrate and having a plurality of integrated circuit devices, whereinat least one of the plurality of integrated circuit devices comprises acapacitor, the capacitor comprising: a first electrode; a secondelectrode; a metal oxide dielectric layer interposed between the firstelectrode and the second electrode; and at least one tungsten oxidebuffer layer, wherein each tungsten oxide buffer layer is interposedbetween the dielectric layer and an electrode selected from the groupconsisting of the first electrode and the second electrode; wherein atleast one electrode selected from the group consisting of the firstelectrode and the second electrode comprises tungsten nitride.
 76. Asemiconductor die, comprising: an integrated circuit supported by asubstrate and having a plurality of integrated circuit devices, whereinat least one of the plurality of integrated circuit devices comprises acapacitor, the capacitor comprising: a first electrode; a tungstennitride second electrode; a metal oxide dielectric layer interposedbetween the first electrode and the second electrode; and a tungstenoxide buffer layer is interposed between the dielectric layer and thesecond electrode.
 77. A semiconductor die, comprising: an integratedcircuit supported by a substrate and having a plurality of integratedcircuit devices, wherein at least one of the plurality of integratedcircuit devices comprises a capacitor, the capacitor comprising: a firstelectrode; a tungsten nitride second electrode; a metal oxide dielectriclayer interposed between the first electrode and the second electrode;and a high temperature annealed, tungsten oxide buffer layer isinterposed between the dielectric layer and the second electrode. 78.The semiconductor die according to claim 77, wherein the hightemperature annealed buffer layer is annealed at least 700 degreesCelsius and has an orthorhomic crystal structure.
 79. A semiconductordie, comprising: an integrated circuit supported by a substrate andhaving a plurality of integrated circuit devices, wherein at least oneof the plurality of integrated circuit devices comprises a capacitor,the capacitor comprising: a first electrode; a second electrode; adielectric layer interposed between the first electrode and the secondelectrode; and a metal oxide buffer layer is interposed between thedielectric layer and the second electrode, wherein the buffer layer hasan orthorhomic crystal lattice structure.
 80. A semiconductor die,comprising: an integrated circuit supported by a substrate and having aplurality of integrated circuit devices, wherein at least one of theplurality of integrated circuit devices comprises a capacitor, thecapacitor comprising: a first electrode; a second electrode; adielectric layer interposed between the first electrode and the secondelectrode; and a metal oxide buffer layer is interposed between thedielectric layer and the second electrode, wherein the buffer layer hasa dielectric constant greater than the dielectric layer.
 81. A memorydevice, comprising: an array of memory cells, wherein at least onememory cell has a capacitor, the capacitor comprising: a firstelectrode; a second electrode; a dielectric layer interposed between thefirst electrode and the second electrode; and at least one metal oxidebuffer layer interposed between the dielectric layer and an electrodeselected from the group consisting of the first electrode and the secondelectrode; a row access circuit coupled to the array of memory cells; acolumn access circuit coupled to the array of memory cells; and anaddress decoder circuit coupled to the row access circuit and the columnaccess circuit.
 82. The memory device according to claim 81, wherein theelectrode selected from the group consisting of the first electrode andthe second electrode has a metal component that is the same as the metalcomponent of the buffer layer.
 83. A memory device, comprising: an arrayof memory cells, wherein at least one memory cell has a capacitor, thecapacitor comprising: a first electrode; a second electrode; adielectric layer interposed between the first electrode and the secondelectrode; and at least one tungsten oxide buffer layer, wherein eachtungsten oxide buffer layer is interposed between the dielectric layerand an electrode selected from the group consisting of the firstelectrode and the second electrode; a row access circuit coupled to thearray of memory cells; a column access circuit coupled to the array ofmemory cells; and an address decoder circuit coupled to the row accesscircuit and the column access circuit.
 84. A memory device, comprising:an array of memory cells, wherein at least one memory cell has acapacitor, the capacitor comprising: a first electrode; a secondelectrode; a metal oxide dielectric layer interposed between the firstelectrode and the second electrode; and at least one tungsten oxidebuffer layer, wherein each tungsten oxide buffer layer is interposedbetween the dielectric layer and an electrode selected from the groupconsisting of the first electrode and the second electrode, wherein atleast one electrode selected from the group consisting of the bottomelectrode of the capacitor and the top electrode of the capacitorcomprises tungsten nitride; a row access circuit coupled to the array ofmemory cells; a column access circuit coupled to the array of memorycells; and an address decoder circuit coupled to the row access circuitand the column access circuit.
 85. A memory device, comprising: an arrayof memory cells, wherein at least one memory cell has a capacitor, thecapacitor comprising: a first electrode; a second electrode; adielectric layer interposed between the first electrode and the secondelectrode; and at least one metal oxide buffer layer interposed betweenthe dielectric layer and an electrode selected from the group consistingof the first electrode and the second electrode, the buffer layer havingan orthorhomic crystalline structure; a row access circuit coupled tothe array of memory cells; a column access circuit coupled to the arrayof memory cells; and an address decoder circuit coupled to the rowaccess circuit and the column access circuit.
 86. A memory device,comprising: an array of memory cells, wherein at least one memory cellhas a capacitor, the capacitor comprising: a first electrode; a secondelectrode; a dielectric layer interposed between the first electrode andthe second electrode; and at least one metal oxide buffer layerinterposed between the dielectric layer and an electrode selected fromthe group consisting of the first electrode and the second electrode,the buffer layer having a dielectric constant greater than thedielectric layer; a row access circuit coupled to the array of memorycells; a column access circuit coupled to the array of memory cells; andan address decoder circuit coupled to the row access circuit and thecolumn access circuit.
 87. A memory device, comprising: an array ofmemory cells, wherein at least one memory cell has a capacitor, thecapacitor comprising: a first electrode; a second electrode; adielectric layer interposed between the first electrode and the secondelectrode; and at least one, high temperature annealed, metal oxidebuffer layer interposed between the dielectric layer and an electrodeselected from the group consisting of the first electrode and the secondelectrode; a row access circuit coupled to the array of memory cells; acolumn access circuit coupled to the array of memory cells; and anaddress decoder circuit coupled to the row access circuit and the columnaccess circuit.
 88. A memory module, comprising: a support; a pluralityof leads extending from the support; a command link coupled to at leastone of the plurality of leads; a plurality of data links, wherein eachdata link is coupled to at least one of the plurality of leads; and atleast one memory device contained on the support and coupled to thecommand link, wherein the at least one memory device comprises: an arrayof memory cells, wherein at least one memory cell has a capacitor, thecapacitor comprising: a first electrode; a second electrode; adielectric layer interposed between the first electrode and the secondelectrode; and at least one metal oxide buffer layer, wherein each metaloxide buffer layer is interposed between the dielectric layer and anelectrode selected from the group consisting of the first electrode andthe second electrode; a row access circuit coupled to the array ofmemory cells; a column access circuit coupled to the array of memorycells; and an address decoder circuit coupled to the row access circuitand the column access circuit.
 89. The module according to claim 88,wherein the electrode selected from the group consisting of the firstelectrode and the second electrode includes a metal component that isthe same as the metal component of the buffer layer.
 90. A memorymodule, comprising: a support; a plurality of leads extending from thesupport; a command link coupled to at least one of the plurality ofleads; a plurality of data links, wherein each data link is coupled toat least one of the plurality of leads; and at least one memory devicecontained on the support and coupled to the command link, wherein the atleast one memory device comprises: an array of memory cells, wherein atleast one memory cell has a capacitor, the capacitor comprising: a firstelectrode; a second electrode; a dielectric layer interposed between thefirst electrode and the second electrode; and at least one tungstenoxide buffer layer, wherein each tungsten oxide buffer layer isinterposed between the dielectric layer and an electrode selected fromthe group consisting of the bottom electrode and the top electrode; arow access circuit coupled to the array of memory cells; a column accesscircuit coupled to the array of memory cells; and an address decodercircuit coupled to the row access circuit and the column access circuit.91. A memory module, comprising: a support; a plurality of leadsextending from the support; a command link coupled to at least one ofthe plurality of leads; a plurality of data links, wherein each datalink is coupled to at least one of the plurality of leads; and at leastone memory device contained on the support and coupled to the commandlink, wherein the at least one memory device comprises: an array ofmemory cells, wherein at least one memory cell has a capacitor, thecapacitor comprising: a first electrode; a second electrode; a metaloxide dielectric layer interposed between the first electrode and thesecond electrode; and at least one tungsten oxide buffer layer, whereineach tungsten oxide buffer layer is interposed between the dielectriclayer and an electrode selected from the group consisting of the firstelectrode and the second electrode, the buffer layer having a dielectricconstant greater than the dielectric layer; a row access circuit coupledto the array of memory cells; a column access circuit coupled to thearray of memory cells; and an address decoder circuit coupled to the rowaccess circuit and the column access circuit wherein at least oneelectrode selected from the group consisting of the bottom electrode ofthe capacitor and the top electrode of the capacitor comprises tungstennitride.
 92. A memory module, comprising: a support; a plurality ofleads extending from the support; a command link coupled to at least oneof the plurality of leads; a plurality of data links, wherein each datalink is coupled to at least one of the plurality of leads; and at leastone memory device contained on the support and coupled to the commandlink, wherein the at least one memory device comprises: an array ofmemory cells, wherein at least one memory cell has a capacitor, thecapacitor comprising: a first electrode; a second electrode; adielectric layer interposed between the first electrode and the secondelectrode; and at least one metal oxide buffer layer, wherein each metaloxide buffer layer is interposed between the dielectric layer and anelectrode selected from the group consisting of the first electrode andthe second electrode, the buffer layer having an orthorhomic crystallinestructure; a row access circuit coupled to the array of memory cells; acolumn access circuit coupled to the array of memory cells; and anaddress decoder circuit coupled to the row access circuit and the columnaccess circuit.
 93. A memory module, comprising: a support; a pluralityof leads extending from the support; a command link coupled to at leastone of the plurality of leads; a plurality of data links, wherein eachdata link is coupled to at least one of the plurality of leads; and atleast one memory device contained on the support and coupled to thecommand link, wherein the at least one memory device comprises: an arrayof memory cells, wherein at least one memory cell has a capacitor, thecapacitor comprising: a first electrode; a second electrode; adielectric layer interposed between the first electrode and the secondelectrode; and at least one, high temperature annealed metal oxidebuffer layer, wherein each metal oxide buffer layer is interposedbetween the dielectric layer and an electrode selected from the groupconsisting of the first electrode and the second electrode; a row accesscircuit coupled to the array of memory cells; a column access circuitcoupled to the array of memory cells; and an address decoder circuitcoupled to the row access circuit and the column access circuit.
 94. Amemory system, comprising: a controller; a command link coupled to thecontroller; a data link coupled to the controller; and a memory devicecoupled to the command link and the data link, wherein the memory devicecomprises: an array of memory cells, wherein at least one memory cellhas a capacitor, the capacitor comprising: a first electrode; a secondelectrode; a dielectric layer interposed between the first electrode andthe second electrode; and at least one metal oxide buffer layer, whereineach metal oxide buffer layer is interposed between the dielectric layerand an electrode selected from the group consisting of the firstelectrode and the second electrode; a row access circuit coupled to thearray of memory cells; a column access circuit coupled to the array ofmemory cells; and an address decoder circuit coupled to the row accesscircuit and the column access circuit.
 95. The system according to claim94, wherein the electrode selected from the group consisting of thefirst electrode and the second electrode includes a metal component thatis the same as the metal component of the buffer layer.
 96. A memorysystem, comprising: a controller; a command link coupled to thecontroller; a data link coupled to the controller; and a memory devicecoupled to the command link and the data link, wherein the memory devicecomprises: an array of memory cells, wherein at least one memory cellhas a capacitor, the capacitor comprising: a first electrode; a secondelectrode; a dielectric layer interposed between the first electrode andthe second electrode; and at least one tungsten oxide buffer layer,wherein each tungsten oxide buffer layer is interposed between thedielectric layer and an electrode selected from the group consisting ofthe first electrode and the second electrode; a row access circuitcoupled to the array of memory cells; a column access circuit coupled tothe array of memory cells; and an address decoder circuit coupled to therow access circuit and the column access circuit.
 97. A memory system,comprising: a controller; a command link coupled to the controller; adata link coupled to the controller; and a memory device coupled to thecommand link and the data link, wherein the memory device comprises: anarray of memory cells, wherein at least one memory cell has a capacitor,the capacitor comprising: a first electrode; a second electrode; adielectric layer interposed between the first electrode and the secondelectrode; and at least one metal oxide buffer layer, wherein each metaloxide buffer layer is interposed between the dielectric layer and anelectrode selected from the group consisting of the first electrode andthe second electrode, the buffer layer having an orthorhomic crystallinestructure; a row access circuit coupled to the array of memory cells; acolumn access circuit coupled to the array of memory cells; and anaddress decoder circuit coupled to the row access circuit and the columnaccess circuit.
 98. A memory system, comprising: a controller; a commandlink coupled to the controller; a data link coupled to the controller;and a memory device coupled to the command link and the data link,wherein the memory device comprises: an array of memory cells, whereinat least one memory cell has a capacitor, the capacitor comprising: afirst electrode; a second electrode; a dielectric layer interposedbetween the first electrode and the second electrode; and at least onemetal oxide buffer layer, wherein each metal oxide buffer layer isinterposed between the dielectric layer and an electrode selected fromthe group consisting of the first electrode and the second electrode,the buffer layer having a dielectric constant greater than thedielectric layer; a row access circuit coupled to the array of memorycells; a column access circuit coupled to the array of memory cells; andan address decoder circuit coupled to the row access circuit and thecolumn access circuit.
 99. A memory system, comprising: a controller; acommand link coupled to the controller; a data link coupled to thecontroller; and a memory device coupled to the command link and the datalink, wherein the memory device comprises: an array of memory cells,wherein at least one memory cell has a capacitor, the capacitorcomprising: a first electrode; a second electrode; a dielectric layerinterposed between the first electrode and the second electrode; and atleast one high temperature annealed, metal oxide buffer layer, whereineach metal oxide buffer layer is interposed between the dielectric layerand an electrode selected from the group consisting of the firstelectrode and the second electrode; a row access circuit coupled to thearray of memory cells; a column access circuit coupled to the array ofmemory cells; and an address decoder circuit coupled to the row accesscircuit and the column access circuit.
 100. An electronic system,comprising: a processor; and a circuit module having a plurality ofleads coupled to the processor, and further having a semiconductor diecoupled to the plurality of leads, wherein the semiconductor diecomprises: an integrated circuit supported by a substrate and having aplurality of integrated circuit devices, wherein at least one of theplurality of integrated circuit devices comprises a capacitor, thecapacitor comprising: a first electrode; a second electrode; adielectric layer interposed between the first electrode and the secondelectrode; and at least one metal oxide buffer layer, wherein each metaloxide buffer layer is interposed between the dielectric layer and anelectrode selected from the group consisting of the first electrode andthe second electrode.
 101. The system according to claim 100, whereinthe electrode selected from the group consisting of the first electrodeand the second electrode includes a metal component that is the same asthe metal component of the buffer layer.
 102. An electronic system,comprising: a processor; and a circuit module having a plurality ofleads coupled to the processor, and further having a semiconductor diecoupled to the plurality of leads, wherein the semiconductor diecomprises: an integrated circuit supported by a substrate and having aplurality of integrated circuit devices, wherein at least one of theplurality of integrated circuit devices comprises a capacitor, thecapacitor comprising: a first electrode; a second electrode; adielectric layer interposed between the first electrode and the secondelectrode; and at least one tungsten oxide buffer layer, wherein eachtungsten oxide buffer layer is interposed between the dielectric layerand an electrode selected from the group consisting of the firstelectrode and the second electrode.
 103. An electronic system,comprising: a processor; and a circuit module having a plurality ofleads coupled to the processor, and further having a semiconductor diecoupled to the plurality of leads, wherein the semiconductor diecomprises: an integrated circuit supported by a substrate and having aplurality of integrated circuit devices, wherein at least one of theplurality of integrated circuit devices comprises a capacitor, thecapacitor comprising: a first electrode; a second electrode; adielectric layer interposed between the bottom electrode and the topelectrode; and at least one metal oxide buffer layer, wherein each metaloxide buffer layer is interposed between the dielectric layer and anelectrode selected from the group consisting of the first electrode andthe second electrode; wherein the metal oxide buffer layer has anorthorhomic crystalline structure.
 104. An electronic system,comprising: a processor; and a circuit module having a plurality ofleads coupled to the processor, and further having a semiconductor diecoupled to the plurality of leads, wherein the semiconductor diecomprises: an integrated circuit supported by a substrate and having aplurality of integrated circuit devices, wherein at least one of theplurality of integrated circuit devices comprises a capacitor, thecapacitor comprising: a first electrode; a second electrode; adielectric layer interposed between the bottom electrode and the topelectrode; and at least one metal oxide buffer layer, wherein each metaloxide buffer layer is interposed between the dielectric layer and anelectrode selected from the group consisting of the first electrode andthe second electrode; wherein the metal oxide buffer layer has adielectric constant greater than the dielectric constant of thedielectric layer.
 105. An electronic system, comprising: a processor;and a circuit module having a plurality of leads coupled to theprocessor, and further having a semiconductor die coupled to theplurality of leads, wherein the semiconductor die comprises: anintegrated circuit supported by a substrate and having a plurality ofintegrated circuit devices, wherein at least one of the plurality ofintegrated circuit devices comprises a capacitor, the capacitorcomprising: a first electrode; a second electrode; a dielectric layerinterposed between the bottom electrode and the top electrode; and atleast one high temperature annealed, metal oxide buffer layer, whereineach metal oxide buffer layer is interposed between the dielectric layerand an electrode selected from the group consisting of the firstelectrode and the second electrode.
 106. A capacitor, comprising: anannealed bottom electrode; a top electrode; a dielectric layerinterposed between the top electrode and the bottom electrode; and anannealed metal oxide buffer layer intermediate the dielectric layer andthe bottom electrode.
 107. A method of forming a capacitor, comprising:forming a bottom electrode layer; annealing the bottom electrode layer;forming a metal oxide buffer layer overlying the bottom electrode layer;annealing the buffer layer; forming a dielectric layer overlying themetal oxide buffer layer; and forming a top electrode layer overlyingthe dielectric layer.
 108. The method of claim 107, further comprisingpatterning the top electrode layer, the buffer layer, the dielectriclayer, and the bottom electrode layer to define the capacitor.
 109. Themethod of claim 108, wherein the method is performed in the orderpresented.
 110. A memory cell comprising a capacitor and an accessdevice, wherein the capacitor includes: a first electrode; a secondelectrode; a dielectric layer interposed between the first electrode andthe second electrode; and a metal oxide buffer layer intermediate thedielectric layer and one of the first and second electrodes.
 111. Thememory cell according to claim 110, wherein the one electrode is atungsten nitride and the buffer layer is a tungsten oxide.
 112. Thememory cell according to claim 110, wherein the buffer layer has aorthorhomic crystalline structure.
 113. A memory cell comprising acapacitor and an access device, wherein the capacitor includes: a firstelectrode; a second electrode; a dielectric layer interposed between thefirst electrode and the second electrode; and a tungsten trioxide bufferlayer interposed between the dielectric layer and one of the first andsecond electrodes.
 114. The memory cell according to claim 113, whereinthe one electrode includes tungsten.
 115. The memory cell according toclaim 114, wherein the buffer layer is grown by oxidizing the oneelectrode.
 116. A memory cell comprising a capacitor and an accessdevice, wherein the capacitor includes: a first electrode; a secondelectrode; a dielectric layer interposed between the first electrode andthe second electrode; and a metal oxide buffer layer interposed betweenthe dielectric layer and one of the first and second electrodes, whereinthe metal oxide buffer layer includes a refractory metal.
 117. Thememory cell according to claim 116, wherein the buffer layer is of theformula MO_(x), and M is a metal component from a group consisting oftungsten, tantalum, zirconium, and hafnium.
 118. A processor and amemory cell electrically connected to said processor, wherein saidmemory cell includes a capacitor comprising: a first electrode; a secondelectrode; a dielectric layer interposed between the first electrode andthe second electrode; and a metal oxide buffer layer intermediate thedielectric layer and one of the first and second electrodes.
 119. Thememory cell according to claim 118, wherein the one electrode is atungsten nitride and the buffer layer is a tungsten oxide.
 120. Thememory cell according to claim 118, wherein the buffer layer has aorthorhomic crystalline structure.
 121. A processor and a memory cellelectrically connected to said processor, wherein said memory cellincludes a capacitor comprising: a first electrode; a second electrode;a dielectric layer interposed between the first electrode and the secondelectrode; and a tungsten trioxide buffer layer interposed between thedielectric layer and one of the first and second electrodes.
 122. Thememory cell according to claim 121, wherein the one electrode includestungsten.
 123. The memory cell according to claim 122, wherein thebuffer layer is grown by oxidizing the one electrode.
 124. A processorand a memory cell electrically connected to said processor, wherein saidmemory cell includes a capacitor comprising: a first electrode; a secondelectrode; a dielectric layer interposed between the first electrode andthe second electrode; and a metal oxide buffer layer interposed betweenthe dielectric layer and one of the first and second electrodes, whereinthe metal oxide buffer layer includes a refractory metal.
 125. Thememory cell according to claim 124, wherein the buffer layer is of theformula MO_(x), and M is a metal component from a group consisting oftungsten, tantalum, zirconium, and hafnium.